1. Field of the Invention
The present invention relates generally to one-time programmable (or OTP) memory devices. Such devices are non-volatile memories, and are in general electrically programmable.
2. Description of the Related Art
The invention relates in particular to a dual-bit OTP device, in other words incorporating a pair of memory cells each capable of storing one bit of information. It also relates to a memory comprising such a memory device, and to methods of writing and reading within such a memory.
In particular, the invention has applications for the storage of information in integrated circuits (ICs). Such information can, for example, be an encryption key used in a chip card of the bank card or similar type, an identification code or, alternatively, a configuration code for such a card, etc.
From the document U.S. Pat. No. 5,553,022, an integrated circuit identification device is known comprising a plurality of memory cells each having an inverter with a MOS transistor of the n type (n-MOS) and a MOS transistor of the p type (p-MOS) in series between two power supply terminals, together with a gate driver coupled to the gate of the n-MOS transistor. In order to program the memory cell, the inverter is permanently modified by inducing the breakdown of the oxide (dielectric) layer that runs between the gate and the substrate (or “bulk”) of the n-MOS transistor. This is achieved by holding the gate at ground potential and applying a high voltage to the bulk. The modified, or otherwise, state of the inverter is monitored during a memory cell read operation, by the detection of the on-state or off-state of the n-MOS transistor when normal voltages for driving this transistor into conduction are applied. The drawback of this prior art is the relatively large number of transistors, namely four, required to form a memory cell.
Now, in integrated circuits, ways of reducing the silicon surface area occupied by the devices are continually being sought, so as to increase the level of integration.